A. Field of the Invention
The present invention relates to a MOS semiconductor device using a silicon carbide semiconductor.
B. Description of the Related Art
A high voltage power device fabricated by using a silicon carbide semiconductor (hereinafter occasionally abbreviated to SiC) is expected to exhibit a far reduced on-state-resistance as compared with a power device fabricated using silicon semiconductor (hereinafter occasionally abbreviated to Si). A MOSFET with a breakdown voltage of 1 to 1.2 kV class has exhibited an on-state-resistance of not greater than 5 mΩ cm2. This on-state-resistance value is less than half that of a MOSFET and an IGBT made of Si for the same breakdown voltage class. If developments for cost reduction and performance improvement progress in the future, it can be expected that most of the IGBTs made of Si for parts of an inverter will be replaced by the ones made of SiC.
The reasons for substantial reduction in on-state-resistance by the use of SiC from that of Si are as follows. Since SiC has a high dielectric breakdown electric field, it can impart a reduced thickness of a voltage blocking layer than Si to attain the same breakdown voltage. In addition, since SiC allows a greater amount of impurity to be doped in the voltage blocking layer, it can reduce resistance in the voltage blocking layer by more than two orders of magnitude than Si.
A breakdown voltage in pn junction diodes, MOSFETs, and IGBTs is retained by a pn junction between a voltage blocking layer of a first conductivity type and a body region of a second conductivity type. As an example, FIG. 8 shows a sectional structure of an essential part of a general trench MOSFET. The trench MOSFET comprises voltage blocking layer 103 of a first conductivity type and body region 105 of a second conductivity type formed in this order by epitaxial growth on one principal surface of SiC substrate 101 of the first conductivity type with a low resistivity (high impurity concentration). Source contact region 106 of the first conductivity type with a high impurity concentration by means of selective ion implantation and body contact region 107 of the second conductivity type with a high impurity concentration for imparting good contact quality by means of selective ion implantation are formed in a portion of a surface region of body region 105. Trench 110 is formed from the surface across source contact region 106 and body contact region 105 reaching voltage blocking layer 103. Gate electrode 112 is embedded in the trench via gate insulation film 111 that is formed on the inner surface of trench 110. Source electrode 123 is formed on the surfaces of source contact region 106 and body contact region 107 in ohmic contact with the surfaces. Source electrode 123 is formed continuously covering gate electrode 112. Electrical insulation between source electrode 123 and gate electrode 112 is ensured by interlayer insulation film 121 interposed between the two electrodes. Drain electrode 122 is formed on the other principal surface of SiC substrate 101 in ohmic contact with the substrate. While the above description is made regarding a MOSFET, an IGBT can be basically constructed by only changing SiC substrate 101 in the MOSFET structure to a substrate of the second conductivity type.
Since a channel for current passage is formed in body region 105 in a MOSFET and an IGBT, an amount of impurity doping (impurity concentration) has a more important effect on channel mobility (a carrier mobility in the channel) and threshold voltage of the gate rather than it does on breakdown voltage. An excessively large amount of impurity doping in body region 105 is undesirable because the threshold voltage grows to an unnecessarily high value and the channel mobility significantly decreases. In view of this issue, an amount of doping in body region 105 cannot be very high. On the other hand, an amount of impurity doping (an impurity concentration) in voltage blocking layer 103 is one to two orders of magnitude higher in SiC than in Si at the same design value of a breakdown voltage. As a result, a depletion layer is liable to extend, in SiC in particular, into body region 105 as well as in the voltage blocking layer 103. A channel length in the structure of a MOSFET or an IGBT as shown in FIG. 8 is a length of a thickness of initial body region 105 before ion implantation less the thickness of source contact region 106, which is the thickness of body region 105 between source contact region 106 and voltage blocking layer 103. A shorter channel length is desirable in order to improve current driving capability per unit area. Therefore, design of an amount of impurity doping and a thickness of body region 105 is extremely important in a structure of a trench MOSFET and a trench IGBT made of SiC.
A diffusion coefficient of impurities in SiC is extremely small, which is different from in Si. As a result, a thermal diffusion process for selective doping of impurities in a confined region to be doped, as employed in Si, requires an extraordinarily high temperature and a very long diffusion time. Consequently, the thermal diffusion process is impractical for a fabrication process. Therefore, an ion implantation process is an indispensable technique for performing selective doping in SiC.
Since a band gap is wide in SiC, practically applicable metals create a type of Schottky contact. A good ohmic contact is necessarily accomplished by forming an ion-implanted region with a high impurity concentration in a surface region of SiC and utilizing tunneling current. Ion implantation must be implemented at a high dose to produce a high impurity concentration in the surface region. Source contact region 106 is made to have a high impurity concentration of not smaller than 3×1019 cm−3 at the surface thereof and a thickness of 0.3 μm to 0.4 μm to obtain the ohmic contact in the trench MOSFET illustrated in FIG. 8.
As is well known with silicon, high dose ion implantation causes severe damage (called implantation damage) on crystals. To recover from this implantation damage, a process of activation annealing is needed. Silicon takes a sole crystal structure in conditions within practical temperature and pressure, and exhibits no crystal transformation. Consequently, a region that is transformed to an amorphous state due to heavy implantation damage is restored to the original crystal structure by the activation annealing. The activation annealing in silicon does not thoroughly restore the original structure yet, particularly in a portion slightly deeper than a designed ion implantation depth (the portion is called a tail) because a light damage rather hinders complete recovery, so that crystal defects remain.
Stating again, the implantation damage caused by low dose ion implantation can be recovered to a practically negligible level by the activation annealing. The low dose implantation, however, does not attain a satisfactory ohmic contact with a metal electrode, increasing an on-state-resistance. Therefore, an ion implantation process at a high dose rate is indispensable.
SiC exhibits a variety of transformations of crystal structures (called “polytype” of SiC, in particular), which causes more complicated problems. It is known, for example, that hexagonal SiC of 4H—SiC and 6H—SiC, types of transformed crystal structures, exhibits higher dielectric breakdown electric field than a cubic SiC of 3C-SiC. However, the hexagonal SiC, when subjected to high dose ion implantation, partially generates the cubic SiC in the process of activation annealing, which inevitably entails a problem of creating crystal defects around the cubic SiC. This problem is known to be controlled by using, for example a {1120} plane, which is perpendicular to a commonly used {0001} plane, in place of the {0001} plane. However, the hexagonal SiC exhibits an especially high dielectric breakdown electric field in a <0001> direction (a dielectric breakdown electric field in a <1120> direction for example, is said to be only 70 to 75% of the one in a <0001> direction). Thus, use of the {1120} plane is disadvantageous in view of tradeoff between a breakdown voltage and an on-state-resistance.
For the SiC consequently, even when a high dose ion implantation is unavoidable to attain a good ohmic contact, a process is commonly employed that alleviates implantation damage to the minimum, for example, an ion implantation process conducted with a wafer held at a high temperature of about 500° C. Unfortunately, such a process still leaves the unavoidable implantation damage in the tail part. No clear knowledge has been acquired heretofore concerning adverse effects of this implantation damage on semiconductor characteristics.
The following documents relate to the above-described conventional technologies. Japanese Unexamined Patent Application Publication No. 2006-303324 discloses a SiC semiconductor device exhibiting an effectively reduced on-state-resistance, by forming an n+-type source layer by ion implantation in a p-type well and a second n-type diffusion layer partially overlapping this source layer to suppress influence of mask misalignment on the on-state-resistance. Japanese Unexamined Patent Application Publication No. 2001-077358 discloses a structure comprising an n-type region on side faces and bottom face of a trench in a trench type SiC MOS semiconductor device. Japanese Unexamined Patent Application Publication No. 2006-147789 discloses a structure comprising an n-region under an n-type source region via a p-region in a silicon carbide MOS field effect transistor.
Since no clear knowledge has been acquired yet concerning adverse effects of the implantation damage induced at the tail part upon ion implantation into a SiC wafer on semiconductor characteristics as describe above, a MOS semiconductor device made of SiC according to a device design based on the conventional knowledge presents a problem that a depletion layer comes in contact with the tail part on application of an off-voltage lowering the breakdown voltage.
The inventors of the present invention have studied the effects of the implantation damage induced in the tail part by ion implantation into SiC on semiconductor characteristics, and found that efficiency percentage, a rate of non-defective products with respect to a breakdown voltage, is substantially affected by an ion implantation process with such a high dose as required for attaining an ordinarily good ohmic contact.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.